Definition of clock latency (clock insertion hold off): In sequential types, just about every timing path is activated by a clock signal that originates from a resource. The flops becoming triggered by the clock sign are known as sinks with the clock. Usually, clock latency (or clock insertion delay) is defined as being the number of time taken because of the clock sign in traveling from its source to the sinks. Clock latency includes of two factors - clock supply latency and clock network latency.

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Supply latency of clock (Source insertion hold off): Supply latency is described since the time taken by the clock sign in traversing from clock resource (could possibly be pLL,oscillator or various other resource) for the clock definition stage. It's often known as resource insertion delay. It may be used to model off-chip clock latency when clock resource is not portion of the chip by itself. Community latency of clock (Network insertion delay): Network latency is outlined as the time taken via the clock sign in traversing from clock definition point to the sinks of the clock. As a result, each and every sink of your clock provides a distinctive network latency. If we speak about the clock, it is going to have:Optimum network latency: Highest of the many network latencies,Least network latency: Minimum amount of each of the network latencies,Typical community latency: Typical of all of the network latencies.

Total clock latency is provided as being the sum of supply latency and network latency. To put it differently, overall clock latency in a level is given as follows:Clock latency = Source latency + Network latency It really is normally mentioned that to get a robust clock tree, ‘sum of supply latency and network latency for all sinks of a clock needs to be equal’. If that is the situation, the clock tree is said to get balanced as this means that every one of the registers are acquiring clock for the identical time; i.e., clock skew is zero.

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