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| Dolphin SMASH v5.8.4 LINUX |
分類: 未分類 |
相姦 綾波優
商品名稱： Dolphin SMASH v5.8.4 LINUX
商品分類： Linux系統專用軟體
商品類型： 混合信號兼顧多層次模擬軟體
語系版本： 英文正式版
運行平台： LINUX (以官方網站為準)
更新日期： 2007-07-02
安裝序號:
序號產生器放至於keygen夾內
內容說明:
混合信號兼顧多層次模擬軟體，能完全符合混合模擬與邏輯訊號電路的需求。 混合訊號指的
是 SMASH 能處理模擬或是連續時間的訊號與不連續時間的訊號， 例如：邏輯(二進位 binary)
或數字(十進位 decimal)。 多層次指的是 SMASH 並沒有被限制在某些 modeling level 上，
即 SMASH 能處理晶體管層次、閘階層次、 功能層次、行為層次並與來自於模擬與邏輯的子電路
加以混合模擬。意味著SMASH 可用在任何層次上的設計作一些精確的電路修正，這表示你將能輕
易處理任何複雜性的電路。另外SMASH有強大的多語言功能，能與 SPICE、Verilog-HDL、
VHDL、ABCD(C-language)與 VHDL-AMS 相容， 可以將模擬區塊以 SPICE 語法描述與數字區塊以
Verilog-HDL 語法或 VHDL 語法描述的設計作多層次混合信號模擬。 SMASH 能快速地模擬驗證
所設計的混合信號晶片，非常適合用來解決混合信號晶片設計問題，以提供高效能的混合信號晶
片設計模擬驗證環境，減化複雜電路模擬驗證的程式，縮短晶片設計的時程。
英文說明:
SMASH 5.8 extends its capabilities for mixed
signalcode-coverage and sensitivity-analysis up to detecting
flawsin Virtual Testbenches and to identifying circuit
weaknessesfor the DfM conscious designer. Improvement on
theblock-busting GUI features facilitate further
theadjustments of speed versus accuracy, as well as
tracing,now augmented for a hierarchical view applicable to
mixedsignal design. With analysis of sensitivity to
dispersion, SMASH provides afast and accurate solution for
the problems of design foryield, manufacturability and
robust design ofnano-electronic analog circuits. Compared to
Monte Carloanalysis, the sensitivity to dispersion is
thousands oftimes faster. Furthermore, the sensitivity to
dispersionanalysis provides the contribution of each
component to thetotal dispersion, thus design debugging
becomes trivial. As SCROOGE enables power consumption
analysis before Place &Route, the SPEF back-annotation now
provides it withparasitic capacitance back-annotation for an
accurate powerconsumption analysis after Place & Route.
Parasiticcapacitances are taken into account to
back-annotate theLiberty wire load model. This allows to
consider the exactrouting capacitance both for cell
interconnection wires andfor clock trees, which represent an
important part of theconsumed power. For increased
interoperability, simulation results can nowbe exported into
standard VCD (Verilog Change Dump) formatfor logic or CSDF
(Common Simulation Data Format) for reusein all compatible
EDA solutions. Of course, SMASH can alsoimport and display
VCD or CSDF results as well as.
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